Verilog Nuts and Bolts: A One Bit Register

In computer science, the way memory is interacted with by the programmer is one of the core lessons that differentiates an undergraduate education from hobbyist tinkering, and confronting the nature of memory is also a major theme in industrial conversations about a piece of code or even an entire programming language. Continue reading →

Verilog Nuts and Bolts: Specifying a Thousand Transistors in One Line

Structural Verilog specifications are very handy for simulation purposes, especially when verification of a large scale system design is needed: you can be certain that all desired transistors are definitely where they need to be if your layout passes LVS, and your Verilog passes your tests.  (You could still have trouble with timing of course!)

But that same Structural Verilog code that validates every logic gate in your design probably isn’t very fit for human consumption, and you definitely don’t want to write it by hand.  You want to specify as much hardware in as little HDL as possible. Continue reading →

Verilog Nuts and Bolts: Modules

Let’s look at an example of a Verilog file that contains some modules.  In the previous demonstration file, I lumped everything together into a single module called “test”.  This is fine for simple modules (by which I mean modules which are simple to describe, not necessarily simple to build), but at scale, organization is handy.  This module will also illustrate a simple example of two different approaches to the same modeling problem. Continue reading →

Verilog and Meaningful Simulations

The best material model of a cat is another, or preferably the same, cat.

–Norbert Wiener

As I start to compile notes for a series on Verilog models, one of the first issues that pops up is that simulation itself isn’t nearly as obvious as it looks on the surface.

This is true of any simulation of anything, of course.  A computer can’t reproduce the physical complexity of the world for anything other than itself, which is rarely that useful.  (One notable exception being testing that computer.)  But with Verilog simulation in particular, there is the issue of it having a malleable level of abstraction.

Continue reading →